1. Field of the Invention
The invention relates generally to the layout and manufacturing process of the semiconductor power devices. More particularly, this invention relates to an improved layout of multiple-stage electrostatic discharge (ESD) protection element integrated with a semiconductor power device to achieve convenient layout, better ESD-leakage trade-offs and more scalable to small die size.
2. Description of the Prior Art
Conventional layout for manufacturing semiconductor power devices with protection circuits against electrostatic discharges (ESD) still has a limitation. A general practice is to place the ESD protection circuits on the gate pad. However, such layout significantly limits the scalability of ESD layout on the semiconductor power device when such devices are required to manufacture on different size of dies for different ESD rating protection applications. Such layout further limits the flexibility of modifying the device configurations. The conventional layout designs also limit the ESD ratings due to the fact that the width of ESD protection device has only limited range of adjustment thus limiting the amount of current that can be redirected by the ESD circuit. Generally speaking, high ESD protection, i.e., ESD circuit with high ESD rating, requires wider ESD width. However, when the ESD circuit is disposed on the gate pad, the ESD width is limited by the size of the gate pad while the size of the gate pad is normally kept as small as possible, usually that is a width just right for wire bonding to provide the gate connection.
FIGS. 1A to 1B are circuit diagrams as disclosed by U.S. Pat. Nos. 4,492,974 and 4,831,424 respectively for a one-stage ESD protection circuit and the one-stage protection circuit with a gate resistor Rg. FIG. 1C is a two stages ESD protection circuit with a gate resistor Rg disclosed by U.S. Pat. No. 6,172,383. These ESD protection circuits are formed with a number of Zener diode pairs for ESD protection without and with Rg as that shown in FIGS. 1D and 1E respectively. As discussed above, the size of the gate pad is generally designed just for wire bonding to provide for gate connection, which should be kept as small as possible. Large gate pad size results in small active area of the same device size. Small active area will cause bad device performance, such as high on-resistance, which means high power consumption. In order to achieve the same device performance, die size increase would be necessary, which causes an increase in production cost. Generally speaking, for the same device performance, e.g., the same power consumption and ESD rating, smaller die size generally can achieve a better performance-to-cost ratio.
For these reasons, the size of the gate pad is typically fixed to a certain size such as 150 um×150 um. With a limited gate pad area, there is no room to adjust the ESD layout, e.g., the adjustment of ESD ratings by adjusting the width of the ESD is limited by the gate pad size.
Recently, there are ever increasing demands to overcome such limitations and difficulties because of the facts that more and more high-speed switching devices are now manufactured on smaller dies for portable device applications. Devices supported on a die that has a larger size usually have high ESD rating even without ESD protection due to its big input capacitance (Ciss). In contrast, a device supported on a die that has smaller size has a low input capacitance thus usually resulting in low ESD rating. For these reasons, device supported on smaller die can be destroyed during human handling due to electric static discharge. Therefore, high ESD rating for small die can significantly increase its reliability. However, for the purpose of saving the die areas in a smaller die, the ESD circuits are generally manufactured on the gate pad to expand the active cell areas thus limiting the ESD layout flexibility and also further limiting the ESD protection ratings for the devices supported on the dies of smaller size. For these reasons, there are strong demands to provide the semiconductor power devices with higher ratings of ESD protections and more flexibility in rearranging the device layout with different die sizes. Particularly, for devices supported on dies of smaller die sizes, there still exist a need to further provide new and flexible ESD circuits on the semiconductor power devices such that the above-discussed limitations can be overcome.
Therefore, it is necessary to provide alternate layout for the ESD circuits on the semiconductor power device not limited by the conventional gate pad ESD configuration while improving the ESD ratings. It is also desirable that the new layout can allow more flexibility for scalability such that the ESD protection can be more conveniently integrated with the semiconductor power devices to provide more effective protections such that the above discussed difficulties and limitations can be overcome.